VCS总结

VCS compile options

options	Descriptions	Comments
-f filename	RTL文件列表
-P pli.tab	定义PLI的列表(Tab)文件	还需要parse定义这些function的c或者cpp
-v file	search for unresolved module references in ‘file’	指定到文件，只parse这一个文件
-y libdir	search for unresolved module references in directory ‘libdir’	VCS looks in this directory for a file with the same name as the module or UDP identifier in the instance，会parse所有文件夹下的文件
+incdir+idir	for `include files, search directory ‘idir’
+libext+extension+	Specifies that VCS searches only for files with the specified file name extensions in a library directory. You can specify more than one extension, separating the extensions with the plus (+)character.	For example, +libext+.v+.V+ specifies searching for files with either the .v or .V extension in a library
-CFLAGS	Passes options to C compiler
-LDFLAGS	Passes flag options to the linker
-full64	Enables compilation and simulation in 64-bit mode
-kdb	When you specify the –kdb option, Unified Compile front end creates the Verdi KDB and dumps the design into the libraries specified in the synopsys_sim.setup file	Unified Compile front end is the integration of VCS and Verdi compilers to unify the compilation flows for simulation and debugging. Unified Compile front end uses VCS compiler scripts to compile the Knowledge Database (KDB) for Verdi.
-ntb_opt	native testbench options : call the build in function in vcs	-ntb_opt uvm-1.2 : call build in uvm lib in vcs
+vcs+flush+all	Increases the frequency of dumping all log files, VCD files, and all files opened by the $fopen system function.
-sverilog	Enables SystemVerilog construcs specified in the IEEE Standard of SystemVerilog, IEEE Std 1800-2009.
-simprofile	profile the cpu and memory status when simulation	see below sections(VCS simprofile)
-timescale	-timescale=time_unit/time_precision
-l	recording the output of compilation to a file	-l vcs.log
-cm line/cond/fsm/tgl/branch/assert	code coverage options	功能覆盖率不需要额外的option
-lca	enable limited customer available feature	These features will be ready for a general release, based on customer feedback and meeting the required feature completion criteria.
-assert enable_hier	Enables the use of the runtime option -assert hier=file.txt, which allows turning assertions on or off.
+v2k	enable verilog2001 相关功能	libmap需要这个options

A typical cmdline for compile (two steps flow) :

VCS_HOME=/home/tools/vcs/xxx \
/home/tools/vcs/xxx/bin/vcs \
+incdir+../src  \
+incdir+../stims  \
../src/list.sv \
../stims/test_list.sv \
-sverilog \
-ntb_opts uvm-1.2 \
-timescale=1ns/1ps \
-full64 \
-kdb \
-debug_access+all \
+libext+.v+.sv+.vt+.gv+.vlib+.svi+.vp \
-l vcs.log

VCS runtime options

options	Descriptions	Comments
-ucli	Unified Command-line Interface (UCLI) provides a common set of commands for interactive simulation. UCLI is the default command-line interface for batch mode debugging in VCS .	simv -ucli -do file.cmds cmd reference : Unified Command Line Interface User Guid
+ntb_delete_disk_cache=value	Specifies whether VCS deletes the disk cache for randomization before simulation.	0 - do not delete. 1 - delete the disk cache (the default condition)
+ntb_random_seed=	Sets the seed value to be used by the top-level random number generator at the start of simulation. The srandom(seed) system function call overrides this setting. The value can be any integer. The default random seed value is 1	seed value >= 1
+ntb_random_seed_automatic	Picks a unique value to supply as the first seed used by a testbench. The value is determined by combining the time of day, host name and process id. This ensures that no two simulations have the same starting seed.	The +ntb_random_seed_automatic seed appears in both the simulation log and the coverage report. When you enter both +ntb_random_seed_automatic and +ntb_random_seed VCS displays a warning message and uses the +ntb_random_seed value.
-assert finish_maxfail=	Terminates the simulation if the number of failures for any assertion reaches N. You must supply N, otherwise no limit is set.	To enable the -assert maxfail and -assert finish_maxfail options at runtime, you must use the ‑assert enable_hier option at compile time.
-assert nopostproc	Disables the display of the SystemVerilog assert and cover statement summary at the end of simulation.	-assert nopostproc+finish_maxfail=1
-skip_translate_body	Tells VCS to omit compilation of Verilog/SystemVerilog/VHDL code between the //synopsys translate_off or /* synopsys translate_off / pragma and the //synopsys translate_on or / synopsys translate_on */ pragma

A typical cmdline for run vcs (two steps flow):

../simv/simv -l testout +ntb_random_seed=1 +UVM_TESTNAME=drvcb_test +uvm_set_verbosity=uvm_test_top.act_env.drv,_ALL_,UVM_HIGH,time 

VCS simprofile

当我们需要优化仿真的时间或者仿真占用的内存时，VCS提供了一个工具(simprofile)用于分析占用的内存和CPU时间。

1. compile option for simprofile

-simprofile

2. run option for simprofile

-simprofile mem/time/noprof

仿真结束后会产生一个整体的报告文件 ： profileReport.html/txt，里面有各种参数的summary

如果需要更进一步详细的报告需要第三步：

3. generate detailed report from database

profrpt simprofile_dir -view mem_all/time_all/ALL -format text/html/ALL -timeline ALL

timeline option 提供了sv dynamic memory的timeline report.可以帮助定位出现问题的时间位置，以及相应代码。

注意，如果报profrpt的版本和simv不一致，需要检查环境变量中的VCS_HOME是否不对，如果不对，需要设置成和simv一致。

VCS libmap

Enable different protions of design hierarchy to use different sets of modules.
同时解决了module name相同的两module被instance在不同的module下，vcs 重名冲突的问题。
可以通过libmap来指定哪些liblist用在哪

libmap.map

library IP_A_LIB /home/ip/ipa/vmod/*.v, /home/ip/ipa1/vmod/*.v
library IP_B_LIB /home/ip/ipb/vmod/*.v, /home/ip/ipb1/vmod/*.v
library IP_C_1_LIB /home/ip/ipc/vmod/*.v

top.config

config topcfg
	design work.top;
	cell IP_A liblist IP_A_LIB;
	cell IP_B liblist IP_B_LIB;
	instance top.u_IP_C.u_IP_C_1 liblist  IP_C_1_LIB;
	default liblist work;
endconfig

vcs cmd line

	vcs +v2k ...
	top.config \
	-top topcfg \
	-libmap ./libmap.map \
	-diag libconfig -libmap_verbose \ 
	...

diag libconfig -libmap_verbose 是debug option，打开可以看到哪些module被map到了哪些lib里进行debug

Verdi

dump 二维数组

$fsdbDumpMDA(<level>,<path>);

第一个参数是dump的层级

• 0: 当前级及其下面所有层级，如top.A, top.A.a，所有在top下面的多维数组均会被dump
• 1: 仅仅dump当前组，也就是说，只dump top这一层的多维数组。

第二个参数为需要dump层级的Hierarchy

Option

-ssv -ssy

以-y -v 加进来的file是不会显示在verdi的hierarchy层次中的，要看到全部信息的话需要使用**-ssv -ssy** 取消掉-v -y的影响。

-ssz

忽略’celldefine编译指令。

-ssf

指定波形文件 wave.fsdb

Examples：

只开simv不加wave

verdi -nologo -ssy -ssv -ssz -simflow -simBin simv

开simv加wave

verdi -simflow -simBin xxx/simv -nologo -ssy -ssv -ssf waves.fsdb

Dump Assertions/Glitch

options	descriptions	comments
NOVAS_FSDB_ENV_MAX_GLITCH_NUM	env options which used to specify glitch dumping default : no record for glitch 0 : record all glitch 1 : the last glitch is stored 2 : the first and the last glitch is stored	setenv NOVAS_FSDB_ENV_MAX_GLITCH_NUM 0
NOVAS_FSDB_ENV_DUMP_SEQ_NUM	env options which used to enable event sequence dumping	setenv NOVAS_FSDB_ENV_DUMP_SEQ_NUM 1