ZYNQ常见错误

  最近在学习FPGA，使用的是ZYNQ7010，因为刚开始，难免会出现各种问题，为了方便以后查阅，在此记录下来常见的错误。
1.变量名字与约束名字不匹配
错误提示：

ERROR: [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 4 out of 134 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led4b_tri_o[3:0].
ERROR: [DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 4 out of 134 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: led4b_tri_o[3:0].
INFO: [Vivado 12-3199] DRC finished with 2 Errors
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
ERROR: [Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
INFO: [Common 17-83] Releasing license: Implementation
ERROR: [Common 17-39] 'write_bitstream' failed due to earlier errors.

拖动滑条看被选中两项的最后边发现：



提示 Problem ports: led4b_tri_o[3:0]，问题出现在引脚上，然后我打开管脚配置图发现，由于自己粗心大意，跟教程上的 led_4b写的不一样:



约束文件由于是直接复制教程的，因此约束条件里的名字跟自己明明的有误：



因此更改约束文件中所有 led_4b_tri_o为 led4b_tri_o或者更改管脚图中的管脚名字即可解决问题。