【HDLBits刷题】【Procedures】Always if2

李十一11

已于 2022-04-07 21:48:34 修改

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分类专栏： HDLBits刷题 Verilog 文章标签： fpga开发

于 2022-04-07 21:37:45 首次发布

原文链接：https://blog.csdn.net/qq_36126787/article/details/62054204

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A common source of errors: How to avoid making latches

When designing circuits, you must think first in terms of circuits:

I want this logic gate
I want a combinational blob of logic that has these inputs and produces these outputs
I want a combinational blob of logic followed by a set of flip-flops

What you must not do is write the code first, then hope it generates a proper circuit.

If (cpu_overheated) then shut_off_computer = 1;
If (~arrived) then keep_driving = ~gas_tank_empty;

Syntactically-correct code does not necessarily result in a reasonable circuit (combinational logic + flip-flops). The usual reason is: "What happens in the cases other than those you specified?". Verilog's answer is: Keep the outputs unchanged.

This behaviour of "keep outputs unchanged" means the current state needs to be remembered, and thus produces a latch. Combinational logic (e.g., logic gates) cannot remember any state. Watch out for Warning (10240): ... inferring latch(es)" messages. Unless the latch was intentional, it almost always indicates a bug. Combinational circuits must have a value assigned to all outputs under all conditions. This usually means you always need else clauses or a default value assigned to the outputs.

Demonstration

The following code contains incorrect behaviour that creates a latch. Fix the bugs so that you will shut off the computer only if it's really overheated, and stop driving if you've arrived at your destination or you need to refuel.

always @(*) begin
    if (cpu_overheated)
       shut_off_computer = 1;
end

always @(*) begin
    if (~arrived)
       keep_driving = ~gas_tank_empty;
end

// synthesis verilog_input_version verilog_2001
module top_module (
    input      cpu_overheated,
    output reg shut_off_computer,
    input      arrived,
    input      gas_tank_empty,
    output reg keep_driving  ); //

    always @(*) begin
        if (cpu_overheated)
           shut_off_computer = 1;
        else
            shut_off_computer = 0;
    end
 
    always @(*) begin
        if (~arrived && ~gas_tank_empty)
           keep_driving = 1;
        else 
            keep_driving = 0;
    end

endmodule

一、锁存器是什么

锁存器是一种在异步时序电路系统中，对输入信号电平敏感的单元，用来存储信息。一个锁存器可以存储1bit的信息，通常，锁存器会多个一起出现，如4位锁存器，8位锁存器。

锁存器在数据未锁存时，输出端的信号随输入信号变化，就像信号通过一个缓冲器，一旦锁存信号有效，则数据被锁存，输入信号不起作用。因此，锁存器也被称为透明锁存器，指的是不锁存时输出对于输入是透明的。

二、锁存器与寄存器的区别：

两者都是基本存储单元，单锁存器是电平触发的存储器，触发器是边沿触发的存储器。本质是，两者的基本功能是一样的，都可以存储数据。意思是说一个是组合逻辑的，一个是在时序电路中用的，时钟出发的。

三、锁存器的危害：

对毛刺敏感，不能异步复位，所以上电以后处于不确定的状态；

Latch会使静态时序分析变得非常复杂；

在PLD芯片中，基本的单元是由查找表和触发器组成的，若生成锁存器反而需要更多的资源。

第三条也是最基本的原因。

四、产生的原因 ********ps重重之重

上面说了那没多只是觉得网上的没把锁存器说明白。下面的才是重点。