HDLBits学习笔记-Dualedge

转载：HDLBits学习笔记—— Dualedge_鸢尾__的博客-CSDN博客

https://blog.csdn.net/Chika__/article/details/124870544


 

难点：FPGA中没有双边沿触发器，因此不能在always块中直接使用"posedge clk or negedge clk"的写法。

转载作者解法：

module top_module (
    input clk,
    input d,
    output q
);
    reg q1,q2;
    always@(posedge clk) begin
        q1<=d;
    end
    always@(negedge clk) begin
        q2<=d;
    end
    assign q = clk?q1:q2;
endmodule

该解法可能会出现毛刺

详见：FPGA中如何实现双边沿采样？_双沿采样_李锐博恩的博客-CSDN博客

官方解法：

module top_module(
	input clk,
	input d,
	output q);
	
	reg p, n;
	
	// A positive-edge triggered flip-flop
    always @(posedge clk)
        p <= d ^ n;
        
    // A negative-edge triggered flip-flop
    always @(negedge clk)
        n <= d ^ p;
    
    // Why does this work? 
    // After posedge clk, p changes to d^n. Thus q = (p^n) = (d^n^n) = d.
    // After negedge clk, n changes to d^p. Thus q = (p^n) = (p^d^p) = d.
    // At each (positive or negative) clock edge, p and n FFs alternately
    // load a value that will cancel out the other and cause the new value of d to remain.
    assign q = p ^ n;
    
    
	// Can't synthesize this.
	/*always @(posedge clk, negedge clk) begin
		q <= d;
	end*/
    
    
endmodule