fpga 2选1选择器和3_8译码器

二选一选择器
源文件：
module mux2(
a,
b,
sel,
out
);
input a;
input b;
input sel;
output out;

assign out =(sel==1)? a:b;

endmodule

Test Bench:

module mux2_tb ();
reg s_a;
reg s_b;
reg sel;
Wire Out;

mux2 mux2_inst0( //前面必须和源文件保持一致，后面的例化名字可以自取
.a(s_a),
.b(s_b),
.sel(sel),
.out(out)
);

initial begin
s_a = 0; s_b = 0; sel = 0;
#200; // 仅用于test benth ，不可用于直接电路 意思为延迟200ns
s_a = 0; s_b = 0; sel = 1;
#200;
s_a = 0; s_b = 1; sel = 0;
#200;
s_a = 0; s_b = 1; sel = 1;
#200;
s_a = 1; s_b = 0; sel = 0;
#200;
s_a = 1; s_b = 0; sel = 1;
#200;
s_a = 1; s_b = 1; sel = 0;
#200;
s_a = 1; s_b = 1; sel = 1;
#200;

end
endmodule

fpga 3_8译码器

源文件：
module decoder_3_8(
a,
b,
c,
out
);
input a;
input b;
input c;
output out;
reg [7:0] out; // 或者二合一 为 output reg [7:0] out;
// 以 always块描述的信号赋值，被赋值象
必须定义为reg类型
always@(*) begin
case({a,b,c}) //{a,b,c} 表示一个三位信号，这
种方式叫做位拼接
3’b000: out = 8’b0000_0001;
3’b001: out = 8’b0000_0010;
3’b010: out = 8’b0000_0100;
3’b011: out = 8’b0000_1000;
3’b100: out = 8’b0001_0000;
3’b101: out = 8’b0010_0000;
3’b110: out = 8’b0100_0000;
3’b111: out = 8’b1000_0000;
endcase
end
endmodule

b 是 描述多位宽信号的格式限制符
b 二进制 3’b101 8’0000_1010
// o 八进制
// d 十进制 3’d5 8’d10
// h 十六进制 4 8’ha

Test Bench
`timescale 1ns/1ns

module decoder_3_8_tb;

reg s_a;
reg s_b;
reg s_c;
wire [7:0] out;

decoder_3_8 decoder_3_8(
.a(s-a),
.b(s-b),
.c(s-c),
.out(out)
);
inintial begin
s_a = 0; s_b = 0;s_c =0;
#200;
s_a = 0; s_b = 0;s_c =1;
#200;
s_a = 0; s_b = 1;s_c =0;
#200;
s_a = 0; s_b = 1;s_c =1;
#200;
s_a = 1; s_b = 0;s_c =0;
#200;
s_a = 1; s_b = 0;s_c =1;
#200;
s_a = 1; s_b = 1;s_c =0;
#200;
s_a = 1; s_b = 1;s_c =1;
#200;

end
endmodule