CTS相关知识点记录1

1、global skew和local skew

global skew：the difference between the longest and shortest clock path

local skew：the worst skew between launch and capture registers of timing paths

2、sink pin、ignore pin、through pin、floating pin

sink pin:

sink pins are also refered to as balancing pins.

sink pins are the clock endpoints that are used for delay balancing. The tool assigns an insertion delay of zero to all sink pins and uses this delay during delay balancing.

During CTS, the tool uses sink pins in calculations and optimizations for both dsign rule contraints and clock tree timing(skew and insertion delay).

包含：

1) a clock pin on a macro cell

2) a clock pin on a sequential cell (a latch or flip-flip), unless that cell drives a generated clock

ignore pin:

ignore pins are clock endpoints that are excluded from clock tree timing  calculations and optimizations. The tool uses ignore pins only in calculations and optimizations for design rule constraints.

During CTS, the tool isolates ignore pins from the clock tree by inserting a guide buffer before the pin. Beyond the ignore pin, the tool never performs skew or insertion delay optimization, but does perform design rule fixing.

包含：

1)source pins of clock trees in the fanout of another clock

2)Nonclock input oins of sequential cells

3)Three-state enable pins

4)output ports

5)Incorrectly defined clock pins 

6)buffer or inverter input pins that held constant by using the set_case_analysis command

7)input pins of combinational cells or integrated clock-gating  cells that do not have any fanout or that do not have any enabled timing arcs

可以利用GUI 来查看sink pin和ignore pin是否被正确定义。

如果没有被正确定义，需要检查timing settings。

如果必须，可以override the default balancing and ignore pin settings by using the set_clock_balance_points command.

through pin(non-stop pin)：

sdc在div_reg/Q创建generated_clock

默认不做balance，即不与其它stop pin做latence的平衡。