Delay Models in Verilog

原文链接：https://hellovlsi.blogspot.com/2014/06/delay-models-in-verilog.html

Delay Models in Verilog

Why delays are required in Verilog simulation?
Functional verification of hardware only tells whether the functionality of design is correct or not. However, in real hardware, logic elements and path have delays associated with them. Therefore, it is also required that design meets timing requirements.

There are three types of delay models used in Verilog simulation - distributed, lumped and pin-to-pin (path) delays. We’ll look into each delay model one by one.

Distributed Delay
Distributed delays are specified on a per element basis. Each individual logic element is assigned a specific delay value. In the two code examples below, it is shown that how delays are specified to individual gates (primitives) and assign statements.

Distributed Delay

Example 1: Distributed Delay applied to individual gates.
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

 //Delay is applied to each gate.
 and #4 a1(e, a, b);
 and #3 a2(f, c, d);
 and #5 a3(out, e, f);
endmodule

Example 2: Distributed Delay applied using assign statement.
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

 //Delay is applied to each assign statement.
        assign #4 e = a & b;
        assign #3 f = c & d;
        assign #5 out = e & f; 
endmodule

Lumped Delay
Lumped delays are specified on a per module basis. They are specified as a single delay on the output gate of the module. The lumped delay takes into consideration the maximum delay from an input to output. From the above, example we can see the maximum delay from input to output is 9 time units (delay from input a to output out), so this delay is mapped to the output gate of the module.

Lumped Delay

Example 3:Lumped Delay Model
module foo (out a, b, c, d);
output out;
input a, b, c, d;

wire e, f;

 //Delay only applied to output gate.
 and a1(e, a, b);
 and a2(f, c, d);
 and #9 a3(out, e, f);
endmodule

Pin-to-Pin Delays
In the pin-to-pin delay model, delays are assigned individually to paths from each input to output. Although pin-to-pin delays may look very detailed, but they are easier for designer, as it requires no knowledge of internals of module. The module may be coded in behavioral statements, data flow, gates, or mixed design. These delays are also known as path delays.

Pin-to-Pin Delay

For the above figure, pin-to-pin delay are specified as follows :

path a-e-out delay = 9
path b-e-out delay = 9
path c-f-out delay = 8
path d-f-out delay = 8

In our next post, we will see how the path delays are specified in Verilog.