名称:投篮游戏VHDL代码Quartus DE1开发板验证(文末获取)
软件:Quartus
语言:VHDL
代码功能:
基于VGA的投篮游戏DE1开发板验证
玩家可以通过拨码开关控制投篮的角度和力度,从而控制篮球进入篮筐,投进得分,数码管显示分数
本代码已在DE1开发板验证,DE1开发板验证如下,其他开发板可以修改管脚适配:
1. 工程文件
2. 程序文件
3. 程序编译
4. RTL图
5. 管脚分配
6. Testbench
7. 仿真图
整体仿真图
游戏控制模块
VGA时序模块
显示模块
部分代码展示:
LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.NUMERIC_STD.ALL; --use IEEE.std_logic_unsigned.all; --use IEEE.std_logic_arith.ALL; --游戏控制 ENTITY game_controller IS PORT ( clk_in,rst : IN STD_LOGIC;--50MHz pixel_clk:OUT STD_LOGIC;--VGA时钟 sw : IN unsigned(7 DOWNTO 0);--SW移动速度 btnL,btnR : IN STD_LOGIC;--按键 hcount : IN unsigned(10 DOWNTO 0); vcount : IN unsigned(10 DOWNTO 0); blank : IN STD_LOGIC;--空白指示 vgaRed: OUT STD_LOGIC_VECTOR(3 downto 0);--RGB vgaBlue: OUT STD_LOGIC_VECTOR(3 downto 0);--RGB vgaGreen: OUT STD_LOGIC_VECTOR(3 downto 0);--RGB receive: OUT STD_LOGIC--投中 ); end game_controller; ARCHITECTURE Behavioral OF game_controller IS COMPONENT key_jitter IS PORT ( clkin : IN STD_LOGIC;--25M key_in : IN STD_LOGIC;--按键输入 key_p : OUT STD_LOGIC--按键上升沿输出 ); END COMPONENT; signal clk: STD_LOGIC := '0'; signal new_frame: STD_LOGIC := '0'; signal left_of_stick : unsigned(10 DOWNTO 0); signal right_of_stick : unsigned(10 DOWNTO 0); signal left_of_ball : unsigned(10 DOWNTO 0); signal right_of_ball : unsigned(10 DOWNTO 0); signal top_of_ball : unsigned(10 DOWNTO 0); signal botton_of_ball : unsigned(10 DOWNTO 0); signal ball_h_move : unsigned(10 DOWNTO 0); signal ball_v_move : unsigned(10 DOWNTO 0); signal dir_up: STD_LOGIC; signal dir_down: STD_LOGIC; signal dir_left: STD_LOGIC; signal dir_right: STD_LOGIC; signal display_stick: STD_LOGIC; signal display_ball: STD_LOGIC; signal display_man: STD_LOGIC; signal move_x : unsigned(4 DOWNTO 0); signal move_y : unsigned(4 DOWNTO 0); signal frame_cnt : unsigned(2 DOWNTO 0); signal top_of_stick : unsigned(10 DOWNTO 0); signal botton_of_stick : unsigned(10 DOWNTO 0); signal use_top_of_stick : unsigned(10 DOWNTO 0); signal use_botton_of_stick : unsigned(10 DOWNTO 0); signal hit: STD_LOGIC := '0'; signal btnL_p: STD_LOGIC := '0'; begin U_key_jitter: key_jitter PORT MAP( clkin => clk,--25M key_in => btnL,--按键输入 key_p => btnL_p--按键上升沿输出 ); receive<=hit; --计数0~3 process (clk_in) begin if (rising_edge(clk_in)) then clk <= not clk;--25MHz end if; end process;
源代码
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