原文链接:https://ewh.ieee.org/soc/es/Nov1997/06/TUTORIAL/MOD3/NOTES/HTML/SLIDE20N.HTM
VHDL can model two types of delay in a component:
- Inertial delay - if two events occur on an input of the component with an interval time less that the defined delay, the output will not reflect either input event, and
- Transport delay - Any event on an input of the component will be reflected on the output.
The default timing type is inertial. If you want to model a transport delay, use the keyword “transport”.
Transport delays are typically used to synchronize timing between VHDL processes and to model systems at high levels where inertial delay effects are ignored.