WIRE4-HDLbits

一、题目要求

        Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:

        创建一个含有三个输入、四个输出可以实现如下连接的模块：

a -> w
b -> x
b -> y
c -> z

        The diagram below illustrates how each part of the circuit corresponds to each bit of Verilog code. From outside the module, there are three input ports and four output ports.

        下图表示了电路的每一个部分如何与Verilog代码的每一位对应。接入到模块外的有：三个输入端口和四个输出端口。

 

        When you have multiple assign statements, the order in which they appear in the code does not matter. Unlike a programming language, assign statements ("continuous assignments") describe connections between things, not the action of copying a value from one thing to another.

        当你有多个assign语句时，他们出现在代码中的顺序并不重要。不像编程语言，assign语句表述了事件间的连接，而非从一个数值赋值到另一个的过程。

        One potential source of confusion that should perhaps be clarified now: The green arrows here represent connections between wires, but are not wires in themselves. The module itself already has 7 wires declared (named a, b, c, w, x, y, and z). This is because input and output declarations actually declare a wire unless otherwise specified. Writing input wire a is the same as input a. Thus, the assign statements are not creating wires, they are creating the connections between the 7 wires that already exist.

        一个潜在的存疑的问题现在澄清：这里绿色的箭头表示了线之间的连接，而其本身并非是线。模块本身已含有7个被定义了的线（命名为a, b, c, w, x, y, 和 z）。这是因为除非另外说明，否则输入和输出间实际上声明了一条线。input wire a等同于input a，因此assign并不是创建了线，他们知识将已存在的线之间创建连接。

---

二、个人实现

module top_module( 
    input a,b,c,
    output w,x,y,z );
    
	assign w=a;
    assign x=b;
    assign y=b;
    assign z=c;
endmodule

---

三、答案

module top_module (
	input a,
	input b,
	input c,
	output w,
	output x,
	output y,
	output z  );
	
	assign w = a;
	assign x = b;
	assign y = b;
	assign z = c;

	// If we're certain about the width of each signal, using 
	// the concatenation operator is equivalent and shorter:
	// assign {w,x,y,z} = {a,b,b,c};
	
endmodule

---

四、分析

	// If we're certain about the width of each signal, using 
	// the concatenation operator is equivalent and shorter:
	// assign {w,x,y,z} = {a,b,b,c};

        如果我们确定每个信号的宽度，我们可以使用assign {w,x,y,z}={a,b,b,c}，其功能等效，代码量更短。同样，即使位宽不一样，如需实现类似的功能，或变量类型一致，则都可以在同一个assign中进行赋值方便维护同时降低代码量。