整数倍数据位宽转换8to16

整数倍数据位宽转换8to16

题目描述
实现数据位宽转换电路，实现8bit数据输入转换为16bit数据输出。其中，先到的8bit数据应置于输出16bit的高8位。

电路的接口如下图所示。valid_in用来指示数据输入data_in的有效性，valid_out用来指示数据输出data_out的有效性；clk是时钟信号；rst_n是异步复位信号。

方法一

`timescale 1ns/1ns

module width_8to16(
	input 				   clk 		,   
	input 				   rst_n		,
	input				      valid_in	,
	input	   [7:0]		   data_in	,
 
 	output	reg			valid_out,
	output   reg [15:0]	data_out
);
    
    reg [1:0] cnt;
    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                cnt <= 2'b0;
            else if(valid_in == 1'b1 && cnt == 2'd1)
                cnt <= 2'b0;
            else if(valid_in == 1'b1)
                cnt <= cnt + 1'b1;
        end
    
    reg [7:0] data_in_reg;
    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                data_in_reg <= 8'b0;
            else if(valid_in == 1'b1)
                data_in_reg <= data_in;
        end
    
    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                data_out <= 16'b0;
            else if(valid_in == 1'b1 && cnt == 2'd1)
                data_out <= {data_in_reg,data_in};
        end
    
    always@(posedge clk or negedge rst_n)
        begin
            if(!rst_n)
                valid_out <= 1'b0;
            else if(valid_in == 1'b1 && cnt == 2'd1 )
                valid_out <= 1'b1;
            else
                valid_out <= 1'b0;
        end
endmodule

方法二：

`timescale 1ns/1ns
 
module width_8to16(
    input                  clk      ,  
    input                  rst_n        ,
    input                     valid_in  ,
    input      [7:0]           data_in  ,
  
    output  reg         valid_out,
    output   reg [15:0] data_out
);
    reg [7:0] data;
    parameter WAIT1 =  1'b0;
    parameter WAIT2  = 1'b1;
 
    reg  cur_state;
    reg  next_state;
     
    always@(posedge clk or negedge rst_n)
        if(!rst_n)
            cur_state <= WAIT1;
        else
            cur_state <= next_state;
     
    always@(*)
    case (cur_state)
        WAIT1: begin
            if(data_in) begin
                next_state = WAIT2;
            end else begin
                next_state = WAIT1;
            end
        end
        WAIT2: begin
            if(data_in)
                next_state = WAIT1;
             else
                next_state = WAIT2;
        end
    endcase
    always@(posedge clk or negedge rst_n)
        if(!rst_n) begin
            data_out <= 16'd0;
            valid_out <= 1'b0;
            data <= 8'd0;
        end else
        case (cur_state)
            WAIT1: begin
                if(valid_in)
                    data <= data_in;
                valid_out <= 1'b0;
            end
            WAIT2: begin
                if(valid_in) begin
                    data_out <= {data, data_in};
                    valid_out <= 1'b1;
                end else
                    valid_out <= 1'b0;
            end
        endcase
 
endmodule