标准单元库---NLDM/CCS library model

最新推荐文章于 2024-10-07 09:38:47 发布

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最新推荐文章于 2024-10-07 09:38:47 发布

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分类专栏：数字后端文章标签： NLDM CCS 标准单元库

本文链接：https://blog.csdn.net/weixin_44726874/article/details/131673777

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Timing Model

数字芯片设计，除了全定制设计外，绝大部分都是基于std cell的半定制设计，那么std cell的模型就极为重要，尤其半定制，需要把一个std cell看成block box，只考虑其input/output pin。其input pin对外部是receiver; output pin对外部是driver。Cell model都需要对receiver/driver分别建立模型，得到的模型结果越接近真实值，则精确度更高。
A timing model consists of driver model, net model and a receiver model. Driver model and receiver models are typically characterized using a circuit simulator, whereas net model is either estimated (wire-load, manhattan or star topology) or extracted from a layout using technology parameters of metal, via and contact etc.

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cell model

集成电路设计是典型的hierarchical design：PMOS/NMOS –> std cell –> design module –> block –> chip。每一次的低层抽象过程，都要抽取出logic和physical信息，以供高层使用。
physical上的抽象，一般是def/lef/frame等，这些都是对GDS的简化
logic上，一般会包括timing、power、noise等信息。
从最底层的MOS管抽象出std cell，就是cell model过程;
从MOS管提取出的timing、power、noise信息写入lib/db file，供上层做STA/SPA/SNA等分析。90nm以前，一般用NLDM/NLPM/NLNM(Nonlinear Delay/Power/Noise Model)。但是advanced node下，NLDM的精确度差，常用的model有:CCS(synopsys) 和 ECS(cadence)。
Block的logic信息也要抽象出来供top使用，常见的抽象block timing模型有：block abstract model(BAM)、extract timing model(ETM)、interface logic models(ILM)等。

NLDM (Non Linear Delay Model)

NLDM用input transition、output capacitance这两参数来查表、插值计算(Z=A+ BX + CY + DXY，四个二元二次方程)得到Cell delay和Output transition

NLDM Driver Mode

NLDM的driver model是一个内阻恒定的电压源（局限性在于先进工艺Rnet远大于内阻时），即输出电压是时间的线性函数，V(t)。
NLDM模型认为cell outout pin从0到1过程中，V是线性地从0到VDD

As seen in the picture, characterization software like guna measure and captures 3 points on sides of active input and active output. These three points are called delay and transition time thresholds.

Difference between input delay threshold and output delay threshold is modeled as cell delay ------cell rise/fall
Difference between lower and upper transition times on output port is modeled as output transition time. —rise/fall transition

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NLDM Receiver Model

NLDM receiver model is simply a single capacitor （由于密勒效应因此不准确） for the entire transition with no sensitivity.

Shortcomings of NLDM model

NLDM only captures 3 output points, which is not sufficient to reflect non-linearities of circuits at lower geometries (65nm and below) in synthesized driver model during static timing analysis. (仅通过3个输出点来评估延时，不够精确)
Classical case of this insufficiency is when driver resistance is order of magnitude（数量级） less than the impedance of net it is driving (Rd << Znet). Driver model requires more granularity in driver model. CCS timing model eliminate need for this synthesis and hence is able to achieve higher accuracy than NLDM.
Other significant shortcoming of NLDM is in the receiver model. NLDM receiver model fails capture miller effect.（MOS管的三极都会存在以下三个电容，分别是：Cgs，Cgd，Cds，米勒电容指的是Cgd，由MOS管的米勒电容引发的米勒效应阻止Vgs电压上升，使得导通时间变长，损耗剧增。）
- This effects dominates delay calculation of STA for very small impedance nets (NLDM的receiver model是单一的input cap，不能捕获Miller效应，对于很小的阻抗网络，Miller效应决定了延迟)
- 对于NLDM receiver model，在advanced node下，Miller效应影响更明显，单一的input cap也无法正确表征。如下图，可以看出在0.6V前后，曲线曲率明显不同，对应cap值分别为23/31，这无法用单一的input cap表示。

  #转换率阈值点
  #
  slew_lower_threshold_pct_fall : 30.0;    
  slew_upper_threshold_pct_fall : 70.0;
  slew_lower_threshold_pct_rise : 30.0;    
  slew_upper_threshold_pct_rise : 70.0;
  
  #延迟阈值点
  #
  input_threshold_pct_fall      : 50.0;        
  input_threshold_pct_rise      : 50.0;        
  output_threshold_pct_fall     : 50.0;      
  output_threshold_pct_rise     : 50.0;
  
  #标准单元库中的转换时间*slew derate = 实际设定的转换率阈值对应的转换时间
  #
  slew_derate_from_library      : 0.5;

CCS (Composite Current Source)

随着工艺节点下降，一些负面效应在advanced node下越来越明显，这些效应也使传统的NLDM model越来越不精确。Synopsys提出了Composite Current Source(CCS)，CCS是基于电流源模型，集timing/power/noise于一体，精确度更高，与SPICE的误差可以达到±2%。
CCS driver model是一个非线性复合电流源，电流随电压和时间而变化，I(t,V)，可以更精确地处理高电感负载。
CCS receiver model是由两个cap值表示，它们随着transition而变化。

为了提供准确的电流矢量模型，CCS会存储波形，且每个波形存储10个电流值和10个时间值，共20个数字。CCS对于每个输入转换和输出负载有20个数字，NLDM对于每个输入转换和输出负载存储2个数字。因此，与NLDM模型相比，CCS模型大小将增加10倍。

CCS Driver Model

CCS driver model is characterized by capturing current waveform flowing into the load capacitor of the cell. CCS driver model also has sensitivity to input transition time, output load and side input states.
CCS driver model is essentially a current source with infinite driver resistance, hence it provides better accuracy in cases where net impedance is very very high. Note, CCS timing model does not require synthesis of driver model, captured current waveform is driver model itself.

CCS Receiver Model

CCS receiver model is characterized much like NLDM receiver model with additional granularity to reflect sensitivities like miller capacitance, state of side inputs, input transition times and output load. To accurately reflect effect of miller capacitance on input capacitance and net-delay, it is divided into two parts - C1 and C2. For STA delay calculation, C1 is used in net delay calculation before receiver waveform hits delay threshold point and C2 is used in net delay calculation after receiver waveform hits delay threshold point.

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CCS receiver model是由两个cap值表示，它们随着transition而变化。C1,C2分别是transition前后半段的cap值。比如input pin的trip points是30%和70%，那么(30%,50%)这段时间的cap值为C1，(50%,70%)这段时间的cap值为C2，STA tool会动态选择cap值。
另外，CCS lib/db里，可以同时含timing/power/noise信息。CCS lib里会看到有ccsn_first_stage/ccsn_last_stage group，分别是最前/后级管子受noise的影响。