#Verilog HDL# Verilog中的ifdef/ifndef/else等用法

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已于 2024-11-24 08:50:04 修改

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分类专栏： Verilog HDL 文章标签： VerilogHDL

于 2024-11-23 19:48:30 首次发布

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通过示例讲解，`ifdef/`ifndef/`elsif/`else/`endif 的用法

示例1：

// Style #1: Only single `ifdef
`ifdef <FLAG>
	// Statements
`endif

// Style #2: `ifdef with `else part
`ifdef <FLAG>
	// Statements
`else
	// Statements
`endif

// Style #3: `ifdef with additional ifdefs
`ifdef <FLAG1>
	// Statements
`elsif <FLAG2>
	// Statements
`elsif <FLAG3>
	// Statements
`else
	// Statements
`endif

示例2：

module tb;
  initial begin

`ifdef MACRO1
    $display ("This is MACRO1");

`elsif MACRO2
    $display ("This is MACRO2");

`endif
  end
endmodule

示例3：

module tb;
  initial begin

`ifndef MACRO1
    $display ("This is MACRO1");

`elsif MACRO2
    $display ("This is MACRO2");

`endif
  end
endmodule

示例4：

module tb;
  initial begin
    `ifdef FLAG
    	$display ("FLAG is defined");
    	`ifdef NEST1_A
    		$display ("FLAG and NEST1_A are defined");
    		`ifdef NEST2
    			$display ("FLAG, NEST1_A and NEST2 are defined");
    		`endif
    	`elsif NEST1_B
    		$display ("FLAG and NEST1_B are defined");
    		`ifndef WHITE
    			$display ("FLAG and NEST1_B are defined, but WHITE is not");
    		`else
    			$display ("FLAG, NEST1_B and WHITE are defined");
    		`endif
    	`else
    		$display ("Only FLAG is defined");
    	`endif
    `else
    	$display ("FLAG is not defined");
    `endif
  end
endmodule