C/verilog语言中的左移与右移，附一道练习题

A 5-bit number 11000 arithmetic right-shifted by 1 is 11100, while a logical right shift would produce 01100.

Similarly, a 5-bit number 01000 arithmetic right-shifted by 1 is 00100, and a logical right shift would produce the same result, because the original number was non-negative.


综上所述:

左移时总是移位和补零,无论是有符号类型数据还是无符号类型数据都统称为逻辑左移。
右移时无符号数是移位和补零，此时称为逻辑右移;
右移时而有符号数大多数情况下是移位和补最左边的位（也就是补最高有效位），移几位就补几位,此时称为算术右移。

题目：

Build a 64-bit arithmetic shift register, with synchronous load. The shifter can shift both left and right, and by 1 or 8 bit positions, selected by amount.
An arithmetic right shift shifts in the sign bit of the number in the shift register (q[63] in this case) instead of zero as done by a logical right shift. Another way of thinking about an arithmetic right shift is that it assumes the number being shifted is signed and preserves the sign, so that arithmetic right shift divides a signed number by a power of two.
There is no difference between logical and arithmetic left shifts.
load: Loads shift register with data[63:0] instead of shifting.
ena: Chooses whether to shift.
amount: Chooses which direction and how much to shift.
2’b00: shift left by 1 bit.
2’b01: shift left by 8 bits.
2’b10: shift right by 1 bit.
2’b11: shift right by 8 bits.
q: The contents of the shifter.

代码：

module top_module(
    input clk,
    input load,
    input ena,
    input [1:0] amount,
    input [63:0] data,
    output reg [63:0] q); 
    always@(posedge clk) begin: shift8
        if(load)
            q <= data;
        else if(ena) begin
            if(amount == 2'b00)
                q <= {q[62:0],1'b0};
            else if(amount == 2'b01)
                q <= {q[55:0],8'b0};
            else if(amount == 2'b10)
                q <= {q[63] == 1'b0 ? 2'b0:2'b11 ,q[62:1]};
            else if(amount == 2'b11)
                q <= {q[63] == 1'b0 ? 9'b0:9'h1ff ,q[62:8]};
        end
    end
endmodule

仿真：