scenario 中rc corner理解

最新推荐文章于 2024-09-12 15:26:29 发布

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最新推荐文章于 2024-09-12 15:26:29 发布

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本文链接：https://blog.csdn.net/hepiaopiao_wemedia/article/details/118054204

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本文介绍了集成电路中四种不同的连接条件——典型、最大电容（MaxC）、最小电容（MinC）、最大RC乘积（MaxRC）和最小RC乘积（MinRC），以及它们如何影响路径延迟。MaxC适用于短路径分析，导致最大延迟；而MinC则适用于最小延迟的短路径分析。对于长路径，MaxRC产生最大延迟，适合最大路径分析；MinRC则产生最小延迟，适合最小路径分析。典型的连接条件通常对平均长度路径的延迟具有极端影响。

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typical: This refers to the nominal values for interconnect resistance and capacitance.

Max C: maximum capacitance. The interconnect resistance is smaller than at typical corner. This corner results in largest delay for paths with short nets and can be used for max path analysis.

Min C: minimum capacitance. The interconnect resistance is larger than at typical corner. This corner results in smallest delay for paths with short nets and can be used for min path analysis.

Max RC: maximum RC product. This results in largest resistance but corresponds to smaller than typical capacitance. Overall, this corner has the largest delay for paths with long interconnects and can be used for max path analysis.

Min RC: minimum RC product. This results in smallest resistance but corresponds to larger than typical capacitance. Overall, this corner has the smallest path delay for paths with long interconnects and can be used for min path analysis.

The path delay using Cworst / Cbest corners is extreme only for short nets while RCworst / RCbest corners is extreme only for long nets. (有木有大佬帮忙解释下，为啥C作用于short path，RC作用于long path？)The typical interconnect corner is often the extreme in terms of path delay for nets with average length. (why? typical is extreme?)

references:

[1] Static Timing Analysis for Nanometer Designs__A Practical Approach

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